Integrated circuits are extremely complex devices, with multiple interrelated and often competing design goals. As integrated circuits have become increasing smaller and faster, an increasing number of the design goals have been discovered to be competing, which tends to require that new techniques, structures, and materials be used in integrated circuit fabrication to overcome the new challenges that arise.
Integrated circuits are typically packaged prior to use, so as to protect the monolithic integrated circuit from damage during subsequent handling or operation. Thus, the package protects the integrated circuit, while also conveniently providing for electrical connections and structural connections to the integrated circuit. Some integrated circuits are electrically connected to the package substrate by a method called wire bonding. A wire bonded integrated circuit is electrically connected to the package substrate to which it is structurally mounted by thin metal wires, such as gold wires.
The wires are bonded to electrically conductive bonding pads on the integrated circuit with a method such as heat or ultrasonic vibration. Regardless of the specific wire bonding method used, a certain amount of pressure is applied by the bonding tip to the bonding pad during the bonding process. If the bonding process is not carefully controlled, or if there are slight variations in the structural strength of the bonding pads or the various layers disposed beneath the bonding pads, then the pressure applied by the bonding tip during the bonding process may be sufficient to crack and otherwise damage the delicate layers of the integrated circuit.
While such damage has always been a problem, the new materials required by modem, denser integrated circuit designs tend to increase the likelihood of such damage. For example, because electrically conductive structures are placed increasingly closer to each other, an increasing problem with parasitic capacitance has arisen. Thus, new electrically insulating materials have been used between the electrically conductive structures, to reduce such capacitance problems. The new electrically insulating materials typically have lower dielectric constants, and thus are generally referred to as low k materials. While low k dielectrics tend to help resolve the capacitance problems described above, they unfortunately tend to introduce new challenges, because they tend to be somewhat softer than the materials that they replaced, and thus have reduced structural strength.
For example, when low k materials are used as dielectrics between a bonding pad and an underlying electrically conductive layer, the pressure exerted by a bonding tip can readily crack the low k layer, resulting in electrical shorts and other problems. In addition, low k materials tend to have lower adhesive properties than the materials they replaced. This tends to increase bonding pad delamination when the probe tip lifts off the bonding pad after a bonding process. Traditionally, failures such as these have been difficult to detect without cross sectioning the integrated circuit. Because such a process is very time consuming, and therefore expensive, and is also destructive, only a relatively low number of integrated circuits could be checked in this manner.
What is needed, therefore, is a system by which integrated circuits can be readily checked in a non destructive manner for defects induced such as during a bonding process, and most especially when low k materials are used as dielectrics between bonding pads and underlying electrically conductive layers.